Digital integrated circuit systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems obey the properties their designers intended. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these integrated circuit systems and the applications which use them become more powerful, detecting and correcting flaws within the systems becomes increasingly difficult.
Achieving the desired level of reliability in a complex system thus depends upon being able to analyze the system's design and characteristics early in the design process. In so doing, the consequences of design choices and trade-offs can be explored and tested prior to design implementation, and potentially disastrous flaws can be detected and remedied while their cost of repair is still relatively inexpensive. For example, detecting a flaw in a highly complex telecommunications integrated circuit prior to its mass fabrication is much more desirable and much more economical than correcting the consequences of the flaw after the circuit has been deployed in systems throughout the world. Electronics engineers and other designers of complex systems use numerous tools to aid in system design, simulation, and debugging.
Simulations play a vital part in the verification stages of integrated circuit development, especially in the case of customized application specific integrated circuits (ASICs), which are designed and brought to market rapidly. Simulation and verification tools are critical to the ASIC development cycle, and other such system development cycles. Hence, an ASIC design is not considered complete until it has been thoroughly simulated and its functionality completely verified.
ASICs are typically designed using some form of HDL (Hardware Description Language), such as VHDL, Verilog, or the like. The functionality and features of an ASIC design are typically embodied as a behavioral model, which describes the behavior of the ASIC. Verification at this stage is done by simulating the ASIC as defined by its behavioral model. The ASIC design is then synthesized using synthesis tools to specific target-libraries, which transform this "behavior" into a "netlist" represented by logic gates in that target-library. Verification at this stage is done by simulating the ASIC as defined by its netlist.
During the verification process, sophisticated simulation algorithms are used to verify the functional blocks of the ASIC. As used herein, each functional block in the design is referred to as an "entity." Verification after netlist synthesis is done by simulating the behavior of the individual gates that make up each entity. All of the entities are connected and interact to model the entire ASIC. The ASIC is typically modeled as a finite system having a finite number of possible states. Each state of the ASIC is represented as a state in a finite state machine. The designer, via the simulation tool, then examines this state machine to determine whether the complex system functions as desired. For example, the designer will examine the set of reachable states of the ASIC model and the transitions between the states to determine whether the ASIC can achieve all of its "desired states" and determine whether the ASIC successfully avoids all "illegal states." A desired state may represent, for example, correctly calculating a desired result. An illegal state may represent, for example, an error condition which results in a malfunction. The goal of the verification process is to determine the set of all reachable states from an initial state of an ASIC model and to use this information to verify the behavior of the ASIC design.
There is a problem, however, when an ASIC design includes one or more internal functional entities, and visibility/observability of that entity is critical to the verification process. One typical such case is where an ASIC design includes an internally embedded microprocessor core which implements many of the design's primary functions and features. The microprocessor implements complex functions of the ASIC. In order properly to verify the ASIC design, the operations of the microprocessor need to be observable. After design synthesis (e.g., into netlists), simulation typically yields only output wave forms for the ASIC design. Whereas a discreet microprocessor can be easily debugged and verified simply by observing the step-executed instructions, understanding, verifying, and debugging the embedded microprocessor ASIC design using only its output wave forms is virtually impossible.
This problem is greatly exacerbated by the geometrically increasing complexity of the latest ASICs. Many of these ASICs include multiple embedded microprocessors which implement very complex algorithms. Such ASICs can result in very complex output wave forms. With the advent of modern technology and growing needs for high-performance speed-intensive complex systems, the number of gates (or gate-count) in an ASIC is growing to a large number. 200,000 gates (approximately 1 million transistors) are quite common in typical ASICs. With 0.15 micron fabrication technology, 45 million gates per chip is predicted to be the order of the future generation of ASICs. For example a modern telecommunications ASIC often includes multiple DSP (digital signal processor) cores and a million or more gates, and processes information in data words of up to 64 bits in one cycle. This, in turn, makes it impossible completely to debug and verify the behavior of the ASIC without access and control of the embedded entities (e.g., DSP cores, microprocessor cores, etc.) of the ASIC simulation.
Thus, what is required is a system which provides for full and complete verification of an ASIC design. What is needed is a system which provides access to the inputs and outputs of embedded entities within a system ASIC. What is needed is a system which allows stepped execution of instructions for the embedded microprocessor or DSP entities of an ASIC during post synthesis simulation. What is further needed is a system which provides a single test interface to a system ASIC during the various abstraction levels of the design process (e.g., behavioral model simulation, netlist simulation, and simulation after place-and-route, etc.). The present invention provides a novel solution to the above requirements.